Nonvolatile semiconductor memory device having verify function

ABSTRACT

A non-volatile semiconductor memory device comprises a flip-flop circuit for holding write data in one of first and second states, a bit line connected to the flip-flop circuit via a switching element, a transistor for charging the bit line, a non-volatile memory cell, connected to the bit line and having a MOS transistor structure, for storing data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode said threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range, and a data setting circuit for connecting one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a non-volatile semiconductormemory device having a rewrite data setting function (i.e. a verifyfunction), and more particularly to a sense amplifier type circuit usedfor write and read operations.

[0003] 2. Description of the Related Art

[0004] Since a non-volatile semiconductor memory device has an advantagein which data is not lost even if power is turned off, a demand for suchnon-volatile semiconductor memories has recently increased more andmore. Unlike a two-transistor byte-type non-volatile semiconductormemory device, a flash memory or an electrically butch-erasablenon-volatile semiconductor memory device may have a memory cellconstituted by a single transistor. As a result, the size of the memorycell can be decreased, and it is expected to substitute the flash memoryfor a large-capacity magnetic disk.

[0005] In this type of non-volatile semiconductor memory device, amemory cell array is constituted by arranging memory cells comprisingMOS transistors with floating gates in a matrix. A threshold value ofthe MOS transistor is varied by accumulating a charge in the floatinggate, and data is stored by the threshold value- At the time of datawrite or data read, an electric current is let to flow to the gateinsulative film to control data. Thus, a write time varies greatly,depending on a change in process or use condition. This is a principaldifference between the above non-volatile semiconductor memory deviceand a DRAM or SRAM. As a result, a single chip may comprise cells with ashort write time and cells with a long write time.

[0006] In order to describe the above problems in detail, a conventionalnon-volatile semiconductor memory device with reference to a NAND typeflash memory.

[0007]FIG. 1 is a circuit diagram showing a cell structure of the NANDtype flash memory. Non-volatile memory cells M1 to M16, each comprisinga MOS transistor having a floating gate, are connected in series. Thememory cell M1 at one end of the group of the memory cells M1 to M16 isconnected to a bit line BL via a selector transistor Q1, and the memorycell M16 at the other end thereof is connected to a common source line Svia a selector transistor Q2. Each transistor constituting each cell isformed on a single well substrate W. Control gates of memory cells M1 toM16 are connected to word lines WL1 to WL16, a control electrode of theselector transistor Q1 is connected to a selector line SL1, and acontrol gate of the selector transistor Q2 is connected to a selectorline SL2.

[0008] Each of the memory cells M1 to M16 has a threshold valuecorresponding to data to be stored. When “0” data is stored, thethreshold value is set at more than 0V and less than 5V. When “1” datais stored, the threshold value is set at less than 0V. (Moreappropriately, these threshold values are set in narrow ranges in orderto provide some margin.)

[0009]FIG. 2 is a graph illustrating a threshold distribution of anN-number of memory cells having threshold values corresponding to theabove data “0” and “1”. In the case of a NAND type flash memory, thestate in which “1” data is stored is normally called “erase state”, andthe state in which “0” data is stored is called “write state”. Anoperation of shifting the threshold value of a memory cell storing “1”data in a positive direction so that the memory cell may store “0” datais called “write operation”. An operation of shifting the thresholdvalue (Vth) of a memory cell storing “0” data in a negative direction sothat the memory cell may store “1” data is called “erase operation”.This definition of operations may differ in the case of NOR type memorydevices.

[0010]FIG. 3 is a table showing voltages to be applied to the memorycells at the time of erase and write operations. In the read operation,the bit line BL is precharged at 5V in a floating state. Then, 5V isapplied to the selector line SL1, 0V is applied to the work line WL ofthe selected memory cell, 5V is applied to the word lines WL of thenon-selected memory cells, 5V is applied to the selector line SL2, 0V isapplied to the well substrate W, and 0V is applied to the common sourceline S. Thus, the transistors of all non-selected memory cells, otherthan the selected memory cell, are turned on. When “0” data is stored inthe selected memory cell, this memory cell is in the non-conductivestate and the bit line potential remains at 5V. If “1” data is stored inthe selected memory cell, this memory cell is in the conductive stateand the bit line potential is discharged and dropped. A data senseoperation is effected by sensing the bit line potential at the time ofread-out.

[0011]FIGS. 4, 5A and 5B show distributions of thresholds of memorycells at the time of erase and write operations. In the erase operation,the bit line BL is opened, 0V is applied to the selector line SL1, 0V isapplied to the word line WL of the memory cell, 0V is applied to theselector line SL2, 18V is applied to the well substrate W, and 18V isapplied to the common source line S. Thus, a tunnel current flows acrossthe floating gate and the well via the gate insulative film, and thethreshold value lowers to 0V or less. FIG. 4 shows a shift of thethreshold value distribution.

[0012] At the time of the write operation, different voltages areapplied in accordance with write data. Specifically, in the case of “0”data write (i.e. in the case of shifting the threshold value), 0V isapplied to the bit line BL. In the case of “1” data write (i.e. in thecase of not shifting the threshold value), 9V is applied to the bit lineBL A potential of 11V is applied to the selector line SL1, 18V isapplied to the word line WL of the selected memory cell, 9V is appliedto the word line WL of the non-selected memory cell, 0V is applied tothe selector line SL2, 0V is applied to the well W, and 0V is applied tothe common source line S. As a result, the selector transistor Q1 andall memory cells M1 to M16 are turned on and set at the same potentialas the bit line potential (no consideration is given to a drop inthreshold value of transistors). Accordingly, in the memory cell inwhich 0V is applied to the bit line BL, a high voltage of 18V is appliedbetween the channel and the control electrode, a tunnel current flows,and the threshold value shifts to the positive side. On the other hand,in the memory cell in which 9V is applied to the bit line BL, only 9V isapplied between the channel and the control electrode. Thus, thethreshold value is not shifted to the positive side. This “9V” is called“write prohibition voltage” . FIGS. 5A and 5B illustrate the shift ofdistribution of these threshold values.

[0013] As stated above, in the non-volatile semiconductor device, awrite operation is effected by using purely physical means of a tunnelcurrent (Fowler-Nordheim tunneling. Thus, the write speed varies frommemory cell to memory cell. Even if the same write time is set, athreshold value of a certain memory cell may fall within a range of 0Vto 5V, but a threshold value of another memory cell may exceed 5V. Thisphenomenon is illustrated in FIG. 6.

[0014] Specifically, “0” data is written in a cell with low write speedat time t1. However, when “0” data is written in a cell with high writespeed, the threshold voltage has exceeded 5V which is an upper limitvalue. As described above, at the time of read-out of the NAND typeflash memory, 5V is applied to the word line of the non-selected memorycell to turn on the word line. If the threshold of a certain memory cellexceeds 5V, data in all memory cells connected in series to this memorycell cannot be read out because the series current path is cut off.

[0015] It is therefore necessary to narrow the distribution ofthresholds to a predetermined value range. In order to keep a sufficientread-out margin, it is desirable to narrow this distribution to asmaller range.

[0016] A bit-by bit verify method has been proposed to solve thisproblem. According to this method, the write time is not made constantfor all memory cells, unlike the above-described technique, anddifferent write times are set for the respective memory cells. Inprinciple, the write time is divided into short time periods, and thefollowing steps are repeated: write→verify→ rewrite dataset→write→verify→rewrite data set . . . . As regards the memory cell thethreshold of which has been sufficiently increased by the verifyoperation, the rewrite data is set so as to prevent the write operationin the next cycle.

[0017] Thus, the cell with high write speed completes the writeoperation earlier, and the threshold thereof will not increaseafterwards (in this case, an increase in threshold due to a potentialdifference of 9V is ignored). FIG. 7 illustrates this technique. Thecell with high write speed completes the write operation at time t0, andthe cell with low write speed completes the write operation at time t1.The threshold values are set near 3.5V.

[0018] The bit-by-bit verify method can be realized most easily bymaking use of an external system such as a CPU or software. However, inthe NAND type flash memory wherein several-thousand bits are writtensimultaneously, it is not practical to input/output several-thousand bitdata by using an I/O interface of 8 bits at most in each verifyoperation. In addition, a several-thousand bit register or comparatorneeds to be provided externally. Accordingly, it is most desirable toperform the verify operation and rewrite data set operation within thechip.

[0019] In a most primitive method for achieving the bit-by-bit verify,it will suffice to provide only the same number of flip-flop circuitsfor latching write data, flip-flop circuits for latching read-out dataand comparators for comparing both write data and read-out data as thenumber of bit lines (several thousand). However, this is impractical.

[0020]FIG. 8 shows schematically a circuit for achieving the bit-by-bitverify operation within the chip. This circuit comprises flip-flopcircuits 1 (1-x; x=1-3) for temporarily storing write data; bit lines BL(BLx; x=1-3); NAND type memory cells 2 (2-x; x=1-3), as illustrated inFIG. 1, connected to the bit lines BL; P-channel transistors Q3 forcharging the bit lines BL; N-channel transistors Q4 for connecting thebit lines BL and flip-flops 1; and N-channel transistors Q5 and Q6connected in series between a power supply potential of 5V and the bitlines BL. The gates of transistors Q5 are connected to bit-line-sideterminals of the flip-flops 1.

[0021] For the purpose of simplicity, FIG. 8 shows the circuitcorresponding to only three bit lines, but in fact there are severalthousand bit lines. A signal line φ1 is connected to the gates of alltransistors Q3, a signal line φ2 is connected to the gates of alltransistors Q6; and a signal line φ3 is connected to the gates of alltransistors Q4. The sources of the transistors Q3 are connected to apower supply having a potential of 9V at the time of write and apotential of 5V at the other time. In addition, a power supply for theflip-flop circuits has a potential of 9V at the time of write and apotential of 5V at the other time.

[0022] The operation of the circuit shown in FIG. 8 will now bedescribed with reference to FIG. 9 showing wave-forms at the time of thewrite operation. Suppose that “0” data is written in the memory cell2-1, “0” data in the memory cell 2-2, and “1” data in the memory cell2-3, and that data is written less easily in the memory cell 2-2 than inthe memory cell 2-1.

[0023] At first, write data supplied from the outside via column gates(not shown) is latched in the respective the flip-flop circuits 1.Specifically, a bit-line-side node N1 of the flip-flop circuit 1-1 isset at 0V, a bit-line-side node N2 of the flip-flop circuit 1-2 is setat 0V, and a bit-line-side node N3 of the flip-flop circuit 1-3 is setat 5V. In this state, a first write operation (WRITE-1) starts.

[0024] At time t10, when the signal line φ1 is set at 0V, thetransistors Q3 are rendered conductive and the bit lines BL are chargedat 9V. Since the power supply for the flip-flop circuits rises to 9V,the node N3 has a potential of 9V.

[0025] At time t11, the potential of signal line φ1 rises to 10V, andthe charge of the bit lines is completed. At the same time, thepotential of signal line δ3 rises to 10V, and the bit lines aredischarged according to the potentials of nodes N (Nx; x=1-3).Specifically, since the potentials of nodes NJ and N2 are 0V, the bitlines BL1 and BL2 are discharged to 0V. Since the potential of node N3is 9V, the bit line BL3 is discharged to 9V. This potential of 9Vfunctions as a write prohibition potential for the memory cell 2-3.Under this condition, a write voltage is applied to each memory cell 2.

[0026] At time t12, the first write operation is completed, and a verifyoperation and a rewrite data set operation (“VERIFY”) start. Thepotential of the signal line φ1 falls to 0V, and the bit lines arecharged at 5V via the transistors Q3. At the same time, since thepotential of the signal line δ3 falls to 0V, the bit lines BL areelectrically disconnected from the flip-flop circuits 1.

[0027] At time t13, the charging for the bit lines is completed, and thebit lines in the floating state are discharged by the memory cells. Thedischarge speed varies depending on the threshold values of the memorycells. If the write operation is not fully effected, the threshold valuedoes not rise and the bit line is discharged. In the first writeoperation, the write operation is not fully effected in either thememory cell 2-1 or memory cell 2-2. Since the write operation for thememory cell 2-3 is not effected, the bit line is necessarily discharged.

[0028] At time t14, the potential of the signal line δ2 rises to 5V.Then, all transistors Q6 are turned on. Since the potentials of nodes N1and N2 are 0V, the corresponding transistors Q5 are non-conductive andthe bit lines BL1 and BL2 are not influenced. Since the potential ofnode N3 is 5V, the bit line BL3 is connected to a power supply potentialof 5V via the transistors Q5 and Q6. As a result, the bit line BL3 ischarged to 5V. This operation is referred to as “recharging of bit lineof ‘0’ data write cell.”

[0029] At time t15, the signal line φ rises to 5V, the bit lines areconnected to the flip-flop circuits, and the bit line potentialsare-latched in the flip-flop circuits. The potentials latched at thenodes N1 to N3 of flip-flop circuits 1 are 0V, 0V and 5V, respectively,from the uppermost node N1. This state remains the same as before thewrite operation.

[0030] At time t20, a second write operation (WRITE-2) starts.Specifically, 9V-charging of the bit lines is effected between time t20and time t21, and data write is effected in the memory cells betweentime t21 and time t22.

[0031] At time t22, second verify and rewrite data set operations areperformed. Specifically, 5V-charging of the bit lines is effectedbetween time t22 and time t23, discharge of the bit lines by the memorycells 2 is effected between time t23 and time t24, and re-charging ofthe bit lines of “0” write cells is stated from time t24. It should benoted that the potential of the bit line BL1 does not substantiallydecrease from 5V. This indicates that the data write in the memory cell2-1 has been completed.

[0032] At time t25, the bit lines are connected to the flip-flopcircuits, and the bit line potentials are latched in the flip-flopcircuits 1. The potentials latched in the nodes N1 to N3 of theflip-flop circuits are 5V, 0V, and 5V, respectively, from the uppermostnode. It should be noted that the potential of the node N1 has changedto 5V from 0V in the first operation.

[0033] The bits in which write is completed are reset from 0V to 5V, andthis 5V is raised to function as 9V-write prohibition voltage. Thus, nofurther write operations are effected in these bits.

[0034] At time t30, a third write operation (WRITE-3) starts.Specifically, 9V-charging of the bit lines is effected between time t30and time t31, and write in memory cells is effected between time t31 andtime t32. It should be noted that the potential of the bit line BL1 is9V. This 9V is the same write prohibition voltage as for the bit lineBL3.

[0035] At time t32, third verify and rewrite data set operations areperformed Specifically, 5V-charging of the bit lines is effected betweentime t32 and time t33, discharge of the bit lines by the memory cells 2is effected between time t33 and time t34, and re-charging of the bitlines of “0” write cells is started from time t34. It should be notedthat the potential of the bit line BL2 does not substantially decreasefrom 5V. This indicates that the data write in the memory cell 2-2 hasbeen completed.

[0036] At time t35, the bit lines are connected to the flip-flopcircuits, and the bit line potentials are latched in the flip-flopcircuits 1. The potentials latched at the nodes N1 to N3 of theflip-flop circuits are 5V, 5V and 5V, respectively, from the uppermostnode. It should be noted that the potential of node N2 has changed to 5Vfrom 0V in the second operation. Thus, all (three bits) write operationshave been completed.

[0037] The operation of the bit-by-bit verify circuit has beendescribed, on the supposition of the ideal case (no interference betweenadjacent bit lines). This circuit, however, has a serious problem, i.e.a malfunction occurs in the verify operation due to interference betweenadjacent bit lines. This problem will now be described.

[0038]FIG. 10 shows realistic wave-forms on the bit lines BL2 and LB3between time t12 and time t15 in FIG. 9. At time t12, the verify andrewrite date set operations start. The bit lines BL2 and BL3 are chargedto 5V via the transistors Q3. Subsequently, charging of the bit lines iscompleted at time t13, and the bit lines in the floating state aredischarged by the memory cells. The write in the memory cell 2-2 is notfully effected, the threshold value does not rise and the bit line BL2is discharged. The bit line BL3 is necessarily discharged.

[0039] At time t14, the recharging of the bit lines of “0” write cellsis performed. Specifically, the bit line BL3 is connected to the powersupply potential of 5V via the transistors Q5 and Q6. As a result, thebit line BL3 is charged to 5V.

[0040] In the meantime, the bit lines extend from end to end of thememory cell array, and the capacitance between adjacent bit lines is notnegligible. Thus, as shown in FIG. 11, floating capacitances C1 and C2occur parasitically. Consequently, when the bit line BL3 is recharged,the potential of the bit line BL2 will rise due to coupling ofcapacitance. If the bit line BL2 is sensed in this state, distinctionbetween the write-completed bit and write-incomplete bit becomesunclear. As a result, the potential of node N of the correspondingflip-flop circuit may be increased to 5V, although the write operationis not completed, and the subsequent write operation may be disabled.

[0041] In order to overcome the above problem, a verify method called“bit line leaking method” has been proposed. According to this method,over the entire verify operation time (time t12 to time t15), thepotential of the signal line φ2 is raised to render the transistors Q6conductive. Thus, the bit line BL3 retains a potential of 5V from thebeginning, and no abrupt change in potential occurs due to recharging.

[0042] Accordingly, no malfunction occurs due to interference betweenthe bit lines. However, since the electric current is kept flowingthrough the conductive cell (memory cell 2-3), power consumptionincreases. Moreover, since the bit line potential at the time thecurrent is kept flowing is determined by division of resistance betweenthe transistors Q5 and Q6 and memory cell 2-3, the bit line potentialcannot perfectly be maintained at 5V and it is stabilized at apredetermined potential below 5V. Thus, recharging cannot be avoided andthe same problem as stated above will occur. Furthermore, the sourcepotential floats due to the leak current of the bit line, and theread-out margin of the read-out cell lowers.

SUMMARY OF THE INVENTION

[0043] The object of the present invention is to provide a non-volatilesemiconductor memory device which can overcome the above drawbacks andachieve a bit-by-bit verify operation without influence due tointerference between bit lines or an increase in power consumption.

[0044] This object can be achieved by a non-volatile semiconductormemory device having a verify mode, the device comprising: bit linemeans; non-volatile memory cell means connected to said bit line means;setting means for setting the bit line means to a reference potential;flip-flop circuit means for holding latch data in one of first andsecond states; coupling means for coupling said flip-flop circuit meansand the bit line means; latch control means for setting the latch datain the flip-flop circuit means in accordance with data to be written insaid memory cell means; and data setting circuit means for forciblyinverting the latch data of the flip-flop circuit means in response tothe reference potential of the bit line means when the referencepotential of the bit line means reaches a predetermined voltage value inthe verify mode for the memory cell means.

[0045] According to the present invention, write data input from outsideis held in the flip-flop circuit in the first state or second state. Asregards the bit of the first state in the flip-flop circuit, a writeoperation is effected in the non-volatile memory cell, and the thresholdis shifted. As regards the bit of the second state in the flip-flopcircuit, the write operation is not effected, and the threshold is notshifted.

[0046] Subsequently, at the time of the verify operation, the data inthe non-volatile memory cell is read out, the charging operation by thesetting means is completed, and the potential bit line in the floatingstate is discharged. When the threshold value of the non-volatile memorycell which performs the write operation falls within the second range ordesirable threshold range, the write operation is completed and the datasetting circuit functioning as forcible inversion means inverts thestate of the flip-flop circuit and maintains the second state. In thiscase, the subsequent write operation for the associated bit is notperformed.

[0047] The threshold of the non-volatile memory cell which performs thewrite operation does not fall within the second range or desiredthreshold range, the first state of the flip-flop circuit is maintained.Accordingly, the subsequent write operation is performed. When data isnot written in the non-volatile memory cell, the second state of theflip-flop is maintained from the beginning. Accordingly, the subsequentwrite operation is not performed.

[0048] As stated above, when the data write is completed by the singlewrite/verify operation, the data in the flip-flop circuit is inverted bythe forcible inversion type data setting circuit. As a result, abit-by-bit verify operation is realized- In addition, unlike the priorart, the bit line potential is not varied, because the bit linepotential is input to only the forcible inversion means. Furthermore,there is neither a need to provide a current through-path, nor anincrease in power consumption.

[0049] Additional objects and advantages of the invention will be setforth in the description which follows, and in part will be obvious fromthe description, or may be learned by practice of the invention. Theobjects and advantages of the invention may be realized and obtained bymeans of the instrumentalities and combinations particularly pointed outin the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The accompanying drawings, which are incorporated in andconstitute a part of the specification, illustrate presently preferredembodiments of the invention, and together with the general descriptiongiven above and the detailed description of the preferred embodimentsgiven below, serve to explain the principles of the invention.

[0051]FIG. 1 is a circuit diagram showing a cell structure of a NANDtype flash memory;

[0052]FIG. 2 illustrates a distribution of threshold values, based onthe number of threshold values of memory cells shown in FIG. 1;

[0053]FIG. 3 is a table showing voltages to be applied to memory cellsat the time of read, erase and write in the memory cells shown in FIG.1;

[0054]FIG. 4 shows a distribution of threshold values having the memorycells at the time of read;

[0055]FIG. 5A shows a distribution of threshold values of the memorycells in a first state at the time of write;

[0056]FIG. 5B shows a distribution of threshold values of the memorycells in a second state at the time of write;

[0057]FIG. 6 is a first characteristic diagram showing a variance inwrite speed among the memory cells;

[0058]FIG. 7 is a second characteristic diagram showing a variance inwrite speed among the memory cells;

[0059]FIG. 8 shows schematically a conventional circuit is for achievinga bit-by-bit verify operation within a semiconductor chip;

[0060]FIG. 9 shows operational wave-forms at the time of write in thestructure shown in FIG. 8;

[0061]FIG. 10 shows realistic wave-forms in a part of the time periodshown in FIG. 9;

[0062]FIG. 11 is a circuit diagram illustrating a problem in thestructure shown in FIG. 8;

[0063]FIG. 12 is a block diagram showing the entire circuitconfiguration of a non-volatile semiconductor memory device according toan embodiment of the present invention;

[0064]FIG. 13 is a circuit diagram showing a main part of a non-volatilesemiconductor memory device according to a first embodiment of theinvention;

[0065]FIG. 14 shows operational wave-forms at the time of write in thecircuit shown in FIG. 13;

[0066]FIG. 15 to FIG. 18 are circuit diagrams showing structuralmodifications of a main part of the first embodiment;

[0067]FIG. 19 is a circuit diagram showing the main part of the firstembodiment in greater detail;

[0068]FIG. 20 is a characteristic diagram showing gmN/gmP dependency ofinverted voltage Vinv;

[0069]FIG. 21 is a characteristic diagram showing a variation in bitline potential Vbit at the time of operation of the circuit shown inFIG. 19;

[0070]FIG. 22 is a circuit diagram showing a main part of a non-volatilesemiconductor memory device according to a second embodiment of theinvention;

[0071]FIG. 23 shows operational wave-forms at the time of read-out inthe circuit shown in FIG. 22;

[0072]FIG. 24 to FIG. 31 are circuit diagrams showing structures offirst to eighth modifications of a main part of the second embodiment;

[0073]FIG. 32 to FIG. 35 are circuit diagrams showing structures offirst to fourth modifications of a main part of a third embodiment;

[0074]FIG. 36 to FIG. 43 are circuit diagrams showing structures offirst to eighth modifications of a main part of a fourth embodiment;

[0075]FIG. 44 is a circuit diagram showing a main part of a non-volatilesemiconductor memory device according to a fifth embodiment of theinvention;

[0076]FIG. 45 to FIG. 48 are circuit diagrams showing structures offirst to fourth modifications of the main part of the fifth embodiment;

[0077]FIG. 49 is a circuit diagram showing a main part of a sixthembodiment of the invention;

[0078]FIG. 50 is a circuit diagram showing a main part of a seventhembodiment of the invention;

[0079]FIG. 51 to FIG. 54 are circuit diagrams showing structures offirst to fourth applied examples of the main part of the firstembodiment;

[0080]FIG. 55 to FIG. 62 are circuit diagrams showing structures offirst to eighth applied examples of the main part of the secondembodiment;

[0081]FIG. 63 to FIG. 66 are circuit diagrams showing structures offirst to fourth applied examples of the main part of the thirdembodiment;

[0082]FIG. 67 to FIG. 74 are circuit diagrams showing structures offirst to eighth applied examples of the main part of the fourthembodiment;

[0083]FIG. 75 to FIG. 78 are circuit diagrams showing structures offifth to eighth applied examples of the main part of the firstembodiment;

[0084]FIG. 79 to FIG. 86 are circuit diagrams showing structures ofninth to 16th applied examples of the main part of the secondembodiment;

[0085]FIG. 87 to FIG. 90 are circuit diagrams showing structures offifth to eighth applied examples of the main part of the thirdembodiment;

[0086]FIG. 91 to FIG. 98 are circuit diagrams showing structures ofninth to 16th applied examples of the main part of the fourthembodiment;

[0087]FIG. 99 to FIG. 102 are circuit diagrams showing structures offirst to fourth applied examples of the main part of the fifthembodiment;

[0088]FIG. 103 to FIG. 106 are circuit diagrams showing structures ofninth to 12th applied examples of the main part of the first embodiment;

[0089]FIG. 107 to FIG. 114 are circuit diagrams showing structures of17th to 24th applied examples of the main part of the second embodiment;

[0090]FIG. 115 to FIG. 118 are circuit diagrams showing structures ofninth to 12th applied examples of the main part of the third embodiment;

[0091]FIG. 119 to FIG. 126 are circuit diagrams showing structures of17th to 24th applied examples of the main part of the fourth embodiment;

[0092]FIG. 127 is a circuit diagram showing the structure of a mostdesirable embodiment of the invention;

[0093]FIG. 128 is a circuit diagram showing a structure of the inventionas applied to a NOR-type EEPROM; and

[0094]FIG. 129 is a characteristic diagram showing a distribution ofthreshold values among NOR-type memory cells.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0095]FIG. 12 is a circuit block diagram showing an entire structure ofa non-volatile semiconductor memory device according to a firstembodiment of the present invention. This semiconductor device of thefirst embodiment is a NAND type flash memory 10. Specifically, thenon-volatile semiconductor memory device 10 comprises a memory cellarray 11, a row decoder 12, sense circuit/write data latches 13, acolumn decoder 14, a column gate 15, a booster circuit 16, a controlcircuit 17 and an I/O buffer 18.

[0096] The memory cell array 11 comprises a plurality of NAND-typememory cells arranged in a matrix, several thousand bit lines BLextending in a column direction, and several thousand word lines WLextending in a row direction. The row decoder 12 selects the word lineon the basis of an address input from the outside. Signal lines of thesense circuit/write data latch 13 are connected at one end to the bitlines and at the other end to the I/O buffer 18 via the column gate 15.The column decoder 14 controls the column gate 15 on the basis of anaddress input from the outside, and selects the bit line and thecorresponding sense circuit/write data latch circuit 13. The boostercircuit 16 supplies high voltages necessary for the write operation anderase operation. The control circuit 17 controls a write operation, anerase operation, a read-out operation, etc. The I/O buffer 18 functionsas interface with the outside of the chip.

[0097] The details of the memory cell within the memory cell array 11are as shown in FIG. 1. Specifically, as shown in FIG. 1, non-volatilememory cells M1 to M16, each comprising a MOS transistor having afloating gate, are connected in series. The memory cell M1 at one end ofthe group of the memory cells M1 to M16 is connected to a bit line BLvia a selector transistor Q1, and the memory cell M16 at the other endthereof is connected to a common source line S via a selector transistorQ2. Each transistor constituting each cell is formed on a single wellsubstrate W. Control gates of memory cells M1 to M16 are connected toword lines WL1 to WL16, a control electrode of the selector transistorQ1 is connected to a selector line SL1, and a control gate of theselector transistor Q2 is connected to a selector line SL2.

[0098] Each of the memory cells M1 to M16 has a threshold valuecorresponding to data to be stored. When “0” data is stored, thethreshold value is set at more than 0V and less than 5V. When “1” datais stored, the threshold value is set at less than 0V. (Moreappropriately, these threshold values are set in narrow ranges in orderto provide some margin.)

[0099]FIG. 2 shows a distribution of threshold values among the memorycells, and FIG. 3 shows the voltages to be applied to the memory cellsat the time of read, erase and write operations.

[0100] In the read operation, the bit line BL is precharged at 5V in afloating state. Then, 5V is applied to the selector line SL1, 0V isapplied to the work line WL of the selected memory cell, 5V is appliedto the word lines WL of the non-selected memory cells, 5V is applied tothe selector line SL2, 0V is applied to the well substrate W, and 0V isapplied to the common source line S. Thus, the transistors of allnon-selected memory cells, other than the selected memory cell, areturned on. When “0” data is stored in the selected memory cell, thismemory cell is in the non-conductive state and the bit line potentialremains at 5V. If “1” data is stored in the selected memory cell, thismemory cell is in the conductive state and the bit line potential isdischarged and dropped. A data sense operation is effected by sensingthe bit line potential at the time of read-out.

[0101] In the erase operation, the bit line BL is opened, 0V is appliedto the selector line SL1, 0V is applied to the word line WL of thememory cell, 0V is applied to the selector line SL2, 18V is applied tothe well substrate W, and 18V is applied to the common source line S.Thus, a tunnel current flows across the floating gate and the well viathe gate insulative film, and the threshold value lowers to 0V or less.

[0102] At the time of the write operation, different voltages areapplied in accordance with write data. Specifically, in the case of “0”data write (i.e. in the case of shifting the threshold value), 0V isapplied to the bit line BL. In the case of “1” data write (i.e. in thecase of not shifting the threshold value), 9V is applied to the bit lineBL. A potential of 11V is applied to the selector line SL1, 18V isapplied to the word line WL of the selected memory cell, 9V is appliedto the word line WL of the non-selected memory cell, 0V is applied tothe selector line SL2, 0V is applied to the well W, and 0V is applied tothe common source line S. As a result, the selector transistor Q1 andall memory cells M1 to M16 are turned on and set at the same potentialas the bit line potential (no consideration is given to a drop inthreshold value of transistors). Accordingly, in the memory cell inwhich 0V is applied to the bit line BL, a high voltage of 18V is appliedbetween the channel and the control electrode, a tunnel current flows,and the threshold value shifts to the positive side. On the other hand,in the memory cell in which 9V is applied to the bit line BL, only 9V isapplied between the channel and the control electrode. Thus, thethreshold value is not shifted to the positive side.

[0103]FIG. 13 is a circuit diagram showing a main part of thenon-volatile semiconductor memory device of the present invention, andspecifically shows circuit portions associated with three bit lines inthe nonvolatile semiconductor memory device 10 shown in FIG. 12. FIG. 13shows only those parts of the memory cell array 11, sense circuit/writedata latches 13, column gate 15 and control circuit 17 shown in FIG. 12,which are necessary for understanding the present invention.

[0104] As is shown in FIG. 13, the circuit associated with one bit linecomprises a flip-flop circuit 1 (1-x; x=1-3) for temporarily storingwrite data; a bit line is BL (BLx; x=1-3); NAND-type memory cells 2(2-x; x=1-3) connected to the bit line BL, as described in connectionwith FIG. 1; a P-channel transistor Q3 for charging the bit line BL; anN-channel transistor Q4 for connecting the bit line BL and flip-flopcircuit 1; and N-channel transistors Q7 and Q8 connected in seriesbetween a 0V-ground potential and a node of the flip-flop circuit 1 onthe opposite side to the bit line BL. The transistors Q7 and Q8constitute forcible inversion means (data setting circuit). The gate ofthe transistor Q7 is connected to the bit line BL.

[0105] The gates of all transistors Q3 are connected to a signal lineφ1. This transistor Q3 constitutes charging unit (19). The gates of alltransistors Q4 are connected to a signal line φ2, and the gates of alltransistors Q8 are connected to a signal line φ3. A part of the controlcircuit 17 is extracted and shown as a clock generating circuit 5. Theclock generating circuit 5 activates the signal lines φ1, φ2 and φ3 atpredetermined timing.

[0106] The sources of the transistors Q3 are connected to a power supplyhaving a potential of 9V at the time of write and a potential of 5V atthe other time. In addition, a power supply for the flip-flop circuitshas a potential of 9V at the time of write and a potential of 5V at theother time.

[0107] The operation of the circuit shown in FIG. 13 will now bedescribed with reference to FIG. 14 showing wave-forms at the time ofthe write operation. Suppose that “0” data is written in the memory cell2-1, “0” data in the memory cell 2-2, and “1” data in the memory cell2-3, and that data is written less easily in the memory cell 2-2 than inthe memory cell 2-1.

[0108] At first, write data supplied from the outside via IO lines/BIOlines (lines of inverted signals of IO) and the column gates 15 islatched in the respective the flip-flop circuits 1. Specifically, abit-line-side node N1 of the flip-flop circuit 1-1 is set at 0V, abit-line-side node N2 of the flip-flop circuit 1-2 is set at 0V, and abit-line-side node N3 of the flip-flop circuit 1-3 is set at 5V. In thisstate, a first write operation (WRITE-1) starts.

[0109] At time t10, when the signal line φ1 is set at 0V, thetransistors Q3 are rendered conductive and the bit lines BL are chargedat 9V. Since the power supply for the flip-flop circuits rises to 9V,the node N3 has a potential of 9V.

[0110] At time t11, the potential of signal line φ1 rises to 10V, andthe charge of the bit lines is completed. At the same time, thepotential of signal line φ2 rises to 10V, and the bit lines aredischarged according to the potentials of nodes N. Specifically, sincethe potentials of nodes N1 and N2 are 0V, the bit lines BL1 and BL2 aredischarged to 0V. Since the potential of node N3 is 9V, the bit line BL3is discharged to 9V. This potential of 9V functions as a writeprohibition potential for the memory cell 2-3. Under this condition, awrite voltage is applied to each memory cell 2.

[0111] At time t12, the first write operation is completed, and a verifyoperation and a rewrite data set operation (“VERIFY”) start. Thepotential of the signal line φ1 falls to 0V, and the bit lines arecharged at 5V via the transistors Q3. At the same time, since thepotential of the signal line φ2 falls to 0V, the bit lines BL aredisconnected from the flip-flop circuits 1.

[0112] At time t13, the charging for the bit lines is completed, and thebit lines in the floating state are discharged by the memory cells. Thedischarge speed varies depending on the threshold values of the memorycells. If the write operation is not fully effected, the threshold valuedoes not rise and the bit line is discharged. In the first writeoperation, the write operation is not fully effected in either thememory cell 2-1 or memory cell 2-2. Since the write operation for thememory cell 2-3 is not effected, the bit line is necessarily discharged.

[0113] At time t14, the potential of the signal line φ3 rises to 5V.Then, all transistors Q8 are turned on. In the first write operation,none of the three memory cells has completed the write operation, andall bit lines are discharged and have low levels. Accordingly, thetransistor Q7 is rendered non-conductive, and the flip-flop circuit 1 isnot influenced at all. In addition, unlike the prior art, the“recharging of bit line of ‘0’ data write cell” is not performed. Thepotentials latched at the nodes N1 to N3 of flip-flop circuits 1 are 0V,0V and 5V, respectively, from the uppermost node N1. This state is thesame as before the write operation.

[0114] At time t20, a second write operation (WRITE-2) starts.Specifically, 9V-charging of the bit lines is effected between time t20and time t21, and data write is effected in the memory cells betweentime t21 and time t22.

[0115] At time t22, second verify and rewrite data set operations areperformed. Specifically, 5V-charging of the bit lines is effectedbetween time t22 and time t23, and discharge of the bit lines by thememory cells 2 is effected between time t23 and time t24. It should benoted that the potential of the bit line BL1 does not substantiallydecrease from 5V. This indicates that the data write in the memory cell2-1 has been completed.

[0116] At time t24, when the potential of the signal line φ3 rises to5V, the transistors Q8 are turned on. Unlike the first operation, thepotential of the bit line BL1 is at high level. Thus, the transistor Q7associated with the bit line BL1 is rendered conductive.

[0117] Then, the node of the flip-flop circuit 1-1, which is opposed tothe bit line BL, is decreased towards the ground potential, and the dataretained in the flip-flop circuit is inverted. In other words, theretained data is inverted by the forcible inversion means. Thepotentials latched in the nodes N1 to N3 of the flip-flop circuit 1 are5V, 0V, and 5V, respectively, from the uppermost node. It should benoted that the data-written bits are reset from 0V to 5V successively.This 5V is raised to function as 9V-write prohibition voltage. Thus, nofurther write operations are effected in these bits.

[0118] At time t30, a third write operation (WRITE-3) starts.Specifically, 9V-charging of the bit lines is effected between time t30and time t31, and write in memory cells is effected between time t31 andtime t32. It should be noted that the potential of the bit line BL1 is9V. This 9V is the same write prohibition voltage as for the bit lineBL3.

[0119] At time t32, third verify and rewrite data set operations areperformed. Specifically, 5V-charging of the bit lines is effectedbetween time t32 and time t33, and discharge of the bit lines by thememory cells 2 is effected between time t33 and time t34. It should benoted that the potential of the bit line BL2 does not substantiallydecrease from 5V. This indicates that the data write in the memory cell2-2 has been completed.

[0120] At time t34, when the potential of the signal line φ3 rises to5V, the transistors Q8 are turned on. Unlike the second operation, thepotential of the bit line BL2 is at high level. Thus, the transistor Q7associated with the bit line BL2 is rendered conductive. Then, the nodeof the flip-flop circuit 1-2, which is opposed to the bit line BL2, isdecreased towards the ground potential, and the data retained in theflip-flop circuit 1-2 is inverted. In other words, the retained data isinverted by the forcible inversion means. The potentials latched in thenodes N1 to N3 of the flip-flop circuit 1 are 5V, 5V, and 5V,respectively, from the uppermost node. It should be noted that thepotential of the node N2 varied to 5V from 0V in the second operation.Thus, the write operations for all bits (three bits) have beencompleted.

[0121] As has been described above, when the data write is completed byevery write and verify operation, the data in the flip-flop circuit isinverted by the forcible inverting means (data setting circuit). Thus,the bit-by-bit verify operation is achieved. Moreover, unlike the priorart, the bit line potential need not be varied, because the bit linepotential is only input to the forcible inverting means. Furthermore, athrough-passage for current is not provided, and power consumption doesnot increase.

[0122] Besides, since the gate of the transistor Q7 is used as a sensenode, the sensitivity is high, and the sense operation is performed withlow voltage.

[0123] FIGS. 15 to 18 are circuit diagrams showing modifications of thefirst embodiment. The circuit shown in FIG. 15 has the same structure asthat shown in FIG. 13, and it is shown for comparison with othercircuits.

[0124] In FIG. 16, the order of transistors Q7 and Q8 is reversed. Avariation in potential of the bit line BL is not transmitted to theflip-flop circuit 1 via a capacitance of the gate/drain of thetransistor Q7, and the data retained in the flip-flop circuit 1 isstabilized. In addition, since the source of the transistor Q7 isgrounded, the flip-flop circuit 1 is inverted with a relatively lowpotential of the bit line BL, as compared to the circuit of FIG. 15. Asa result, the stable verify operation can be effected, and possibilityof error of the verify operation is reduced. (Inversely, in FIG. 15, ascompared to FIG. 16, switching noise of the transistor Q8, which mayadversely affect the flip-flop circuit, is cut off by the transistor Q7,and therefore erroneous inversion of the flip-flop circuit due to noisecan be prevented.)

[0125] In FIG. 17, transistors Q8, Q7 and Q82 are connected in series,and the transistors Q81 and Q82 function as the transistor Q8 in FIG.15. Accordingly, the advantages of both circuits shown in FIGS. 15 and16 can be enjoyed, the stable verify operation is performed, and theerroneous inversion of the flip-flop circuit can be prevented.

[0126] In FIG. 18, the transistor Q8 shown in FIG. 15 is replaced bytransistors Q91 and Q92. Complementary signals φ3 and B100 3 are inputto the transistors Q91 and Q92. Specifically, when the potential ofsignal φ3 rises to 5V, the transistor Q91 is turned on and the flip-flopcircuit 1 is forcibly inverted according to the potential of the bitline BL. If the potential of signal Bφ3 changes to 0V, the transistorQ92 is turned on and the gate potential of the transistor Q7 is set atground potential of 0V. Since the transistors Q91 and Q92 are operatedonly by transfer of charge, the size thereof may be small. Accordingly,the area of the device can be made less than that in theseries-connected transistor construction shown in FIGS. 15 to 17. Sinceboth circuits operate similarly with the circuit of FIG. 13, Adescription of the details of the operation may be omitted.

[0127] Conditions for maintaining stability of the operation in theabove-described first embodiment will now be described. FIG. 19 is acircuit diagram for illustrating in greater detail the flip-flop circuit1-1 transistors Q4, Q7 and Q8 in FIG. 13. The flip-flop circuit 1-1 isconstituted by connecting in parallel in opposite directions an invertercomprising a P-channel transistor Q01 and an N-channel transistor Q02and an inverter comprising a P-channel transistor Q03 and an N-channeltransistor Q04. It is the transistor Q01 that charges a node N01connected to the transistors Q7 and Q8 functioning as forcible inversionmeans. An important factor for the stable operation is the magnitude ofconductance of the transistor Q01 and the transistors Q7 and Q8.

[0128] Suppose that the conductance of the transistor Q01 is gmP and theequivalent conductance of the series-connected transistors Q7 and Q8 isgmN. FIG. 20 shows a simulation result of the gmN/gmP dependency of aninversion voltage vinv (a minimum voltage value which needs to beapplied to the bit line when the flip-flop is inverted) at the time Vcc(power supply voltage) is 5V. The inversion voltage vinv decreasessteeply in the vicinity of gmN/gmP=1 and approaches gradually to thethreshold value Vth of the transistors Q7 and transistor Q8. Even in thecase where an input signal or bit line potential Vbit is precharged to,e.g. Vcc and then the conductance of the cell comes into free-running inan ideal “0” state (“0” cell read-out), the bit line potential Vbit isinfluenced by the capacitance between adjacent bit lines (according tothis embodiment a problem of influence of capacitance between adjacentbit lines at the bit line charging time after the verify operation canbe solved, but a problem of influence of capacitance at the time offree-running remains unsolved). If the potential of one of the adjacentbit lines decreases, the bit line potential vbit decreases, as shown inFIG. 21. Specifically, when a “0” cell is connected to both-side bitlines, substantially no decrease occurs in potential vbit across thesebit lines. However, if a “1” cell is connected to either or both-sidebit lines, a decrease occurs in bit line potential vbit. Thus, in orderto surely sense “0” in the bit line with decreased potential, it isdesirable that potential vinv be low. In FIG. 20, from a point at whichthe gmN/amP exceeds 1.8, the gmN/gmP dependency of inversion voltagedecreases steeply and approaches a low vth. Accordingly, it is desirablethat the value of gmN/gmP be 1.8 or above. As a result, the operation ofthe flip-flop is stabilized, and a circuit hardly susceptible tofluctuation in power supply voltage, noise, etc. can be obtained. Inaddition, by setting this value as described above, the inversionvoltage can be set with little influence of conductance fluctuation dueto misalignment of masks and a fluctuation in gmN/gmP. These merits inmanufacture can also be enjoyed.

[0129] In brief, the above advantages can be obtained if the equivalentconductance gmN of the series-connected MOS transistors serving asforcible inversion means and the conductance gmP of the MOS transistorfor charging/discharging the junction node in the flip-flop circuit meetthe formula:

gmN/gmP>1.8  (i)

[0130]FIG. 22 is a circuit showing a second embodiment of the presentinvention. The circuit elements common to those in the first embodimentare denoted by like reference numerals. A circuit portion associatedwith one bit line comprises a flip-flop circuit 1 for temporarilystoring write data; a bit line BL, a NAND-type memory cell 2(illustrated in FIG. 1) connected to the bit line BL; a P-channeltransistor Q3 for charging the bit line BL; a transistor Q4 forconnecting the bit line BL and the flip-flop circuit 1; and transistorsQ7 and Q8 connected in series between the node of the flip-flop circuit1, which is located on the opposite side of the bit line BL, and theground potential of 0V.

[0131] The transistors Q7 and Q8 constitute forcible inversion means(data setting circuit). The gate of the transistor Q7 is connected tothe bit line BL. The gates of all transistors Q3 are connected to asignal line φ1. This transistor Q3 constitutes charging means. The gatesof all transistors Q4 are connected to a signal line φ2, and the gatesof all transistors Q8 are connected to a signal line φ3. The secondembodiment differs from the first embodiment in that transistors Q10having gates connected to a signal line δR are connected between nodes Nof flip-flop circuits 1 and the ground potential. The transistor Q10constitutes reset means. A part of the control circuit 17 is extractedand shown as clock generating circuit 6 for driving the signal lines φ1,φ2, φ3 and φR at predetermined time, as described later

[0132] The sources of the transistors Q3 are connected to a power supplyhaving a potential of 9V at the time of write and a potential of 5V atthe other time. In addition, a power supply for the flip-flop circuitshas a potential of 9V at the time of write and a potential of 5V at theother time.

[0133] With reference to FIG. 23 showing operational wave-forms at thetime of read-out, the operation of the circuit shown in FIG. 22 will nowbe described. At time t0, the potential of the signal line φ1 lowers andthe bit line BL is precharged at 5V. At the same time, the potential ofthe signal line φR rises and the flip-flop circuit 1 is reset. That is,the node N is set at 0V. At time t2, the potential of the signal line φ1rises and the bit line BL is set in the floating state. The bit line BLis discharged by the data retained in the memory cell 2. When thepotential of signal line φ3 rises at time t2, the transistor Q8 isturned on and the flip-flop 1 is forcibly inverted by the transistor Q7in accordance with the value of the bit line potential.

[0134] By adding only one transistor Q10 in the first embodiment, theread-out operation can be effected through the same path as in theverify operation. Accordingly, the verify operation and the read-outoperation correspond to each other exactly, and a circuit lesssusceptible to a fluctuation in power supply voltage, noise, etc. can berealized.

[0135] Furthermore, since the detection (sense) level of the bit linepotential at the time of read-out can be set by controlling thethreshold value of the transistor Q7, the detection can be effected witha lower potential than in the prior art (i.e. the detection using thethreshold of the inverter). In other words, since the sense level islow, pre-charge up to vcc is not necessary, unlike the prior art. As aresult, the power supply potential can be decreased, and therefore thereliability of the circuit is enhanced.

[0136] FIGS. 24 to 31 are circuit diagram showing various modificationsof the second embodiment. FIG. 24 shows the same structure as FIG. 22,and FIG. 24 is prepared for the purpose of reference. FIG. 24 to FIG. 27show examples in which N-channel transistors Q10 are connected tobit-line-side nodes of the flip-flop circuits 1, and FIG. 28 to FIG. 31are examples in which P-channel transistors Q11 are connected to thenodes of the flip-flop circuits, which are located on the opposite sideto the bit lines. Each of these examples functions similarly with thesecond embodiment, and therefore a description thereof is omitted.

[0137]FIG. 32 to FIG. 35 are circuit diagram showing a third embodimentof the invention, wherein the bit line potential is sensed via aninverter 80 or a NAND gate 81, thereby driving a transistor Q80 forforcible inversion. Unlike the first embodiment, the bit line (BL)-sidenode of the flip-flop circuit 1 is forcibly inverted by the transistorQ80. Thus, a sensing circuit with higher sensitivity can be realized bythe inverter 80.

[0138]FIG. 36 to FIG. 43 are circuit diagrams showing a fourthembodiment of the invention, wherein a reset transistor driven by signalφR or BφR is provided in the third embodiment. The operation of thefourth embodiment is similar to that of the second embodiment, and adescription thereof is omitted.

[0139]FIG. 44 is a circuit diagram showing the structure of a fifthembodiment having a butch verify function. In the first embodiment, noconsideration is given of the detection of completion of data write inall bits. For example, the nodes (M1 to N3) of the flip-flop circuitsare successively sensed, and if 5V is latched in all bits, the datawrite is completed. A circuit for sensing the nodes in a butch manner isreferred to as “butch verify circuit.”

[0140] The butch verify circuit comprises transistors Q201, 202 and 203,a transistor Q21 and an inverter 20, as shown in FIG. 20. Specifically,a circuit portion associated with one bit line comprises a flip-flopcircuit 1 for temporarily storing write data; a bit line BL, a NAND-typememory cell 2 (illustrated in FIG. 1) connected to the bit line BL; aP-channel transistor Q3 for charging the bit line BL; a transistor Q4for connecting the bit line BL and the flip-flop circuit 1; andtransistors Q7 and Q8 connected in series between the node BN (BN1 toBN3) of the flip-flop circuit 1, which is located on the opposite sideof the bit line BL, and the ground potential of 0V The transistors Q7and Q8 constitute forcible inversion means (data setting circuit). Thegate of the transistor Q7 is connected to the bit line BL.

[0141] The gates of all transistors Q3 are connected to a signal lineφ1. This transistor Q3 constitutes charging means. The gates of alltransistors Q4 are connected to a signal line φ2, and the gates of alltransistors Q8 are connected to a signal line φ3. The source of thetransistor Q3 is connected to a power supply source having a potentialof 9V at the time of write and having a potential of 5V at the othertime. A power supply for the flip-flop circuit has a potential of 9V atthe time of write and a potential of 5V at the other time. A part of thecontrol circuit 17 is extracted and shown as clock generating circuit 8for driving signal lines φ1, φ2, φ3 and φ5 at predetermined time.

[0142] The principle of the verify operation is the same as that in thefirst embodiment. The detection of completion of data write in all bitsis performed as follows. Specifically, after the verify operation iscompleted, the signal φ5 is lowered and a common verify line 26 isprecharged to 5V. If any one of the transistors Q201 to Q203 is turnedon and rendered conductive, the common verify line 26 is discharged. Ifall transistors Q201 to Q203 are turned off and rendered non-conductive,the potential of the common verify line 26 remains 5V

[0143] The transistors Q201 to Q203 are connected to the nodes BN of theassociated flip-flop circuits 1, which are located on the side oppositeto the nodes N. Accordingly, if the potential of node N is 5V, thepotential of node BN is 0V and the transistors Q201 to Q203 are renderednon-conductive. If the potential of node N is 0V, the potential of nodeBN is 5V and the transistors Q201 to Q203 are rendered conductive.

[0144] As a result, if any one of the bit lines associated with nodes N1to N3 has a potential of 0V after the verify operation (i.e. if thewrite operation has not been completed), the common verify line 26 isdischarged and the output VFY becomes 5V. If the potentials of all nodesN1 to N3 reaches 5V after the verify operation (i.e. if the data writefor all bits is completed), the common verify line 26 remains at 5V andthe output VFY becomes 0V.

[0145] As described above, if the butch verify circuit is provided inthe fifth embodiment, it is possible to detect the completion of datawrite for all bits in a butch manner. It is therefore possible todetermine the timing for halting the write operation and the verifyoperation. In the fifth embodiment, the write operation and verifyoperation may be repeated until the output VFY reaches 0V.

[0146] If the butch verify circuit is combined with the above-mentionedforcible inversion type sense amplifier, the verify time can bedecreased. For example, in FIG. 44, as regards the latch data in theflip-flop circuit 1 in the forcible inversion type sense amplifier, thenode N is at “H” level and the node BN is at “L” level before the verifyoperation. Thus, all transistors Q201 to Q203 are turned off.Accordingly, the timing for charging the common verify line 26 by signalφ5 can be set during or before the verify read-out operation. In thevarious sense methods described in connection with the prior art, it isnecessary to charge the common verify line 26 after the verify read-outoperation is completed. However, in the present embodiment, the commonverify line can be charged high a higher timing, and therefore the butchverify time and, accordingly, the write time can be decreased.

[0147]FIG. 45 to FIG. 48 are circuit diagrams showing main parts ofvarious modifications of the fifth embodiment. FIG. 45 shows the samestructure as FIG. 44, FIG. 45 is prepared for the purpose of comparison.FIG. 46 shows an example wherein the butch verify circuit is constitutedby connecting P-channel transistors Q21x (x=1, 2, 3) in series. FIG. 47shows an example wherein a butch verify circuit comprising the sameN-channel transistor Q20x (x=1, 2, 3) as shown in FIG. 45 is provided onthe node (N)− side of the associated flip-flop circuit 1. FIG. 48 showsan example wherein the same P-channel transistor Q21x (x=1, 2, 3) asshown in FIG. 46 is connected to the node N side of the associatedflip-flop circuit 1, thereby constituting the butch verify circuit. Thecircuits of these examples operate similarly with the circuit shown inFIG. 44, and a detailed description of the operation is omitted.

[0148] In FIGS. 45 and 48, since all sense transistors for discharge areconnected in parallel, the butch verify operation can be effected athigher speed than in the other circuits. In the examples of FIGS. 46 and47, since the sense transistors are connected in series, the chip areacan be reduced. The example shown in FIG. 45 is optimal, and the speedof the circuit operation is higher than that in FIGS. 46 to 48, byvirtue of the parallel connection and the use of N-channel transistors.

[0149]FIGS. 49 and 50 are circuit diagrams showing sixth and seventhembodiments of the invention, respectively. In these examples, a singleflip-flop circuit 1 is shared by a plurality of bit lines. The circuitshown in FIG. 49 comprises a flip-flop circuit 1; bit lines BLL and BLRconnected to the flip-flop circuit 1; a first verify read-out circuit 61controlled by signals φ11, φ12 and φ13; and a second verify read-outcircuit 62 controlled by signals φ21, φ22 and φ23. The flip-flop circuit1 can be shared by the bit lines BLL and BLR, and the pattern area canbe reduced.

[0150] In the seventh embodiment shown in FIG. 50, a single flip-flopcircuit 1 is shared by bit lines BL1, BL2, BL3 and BL4. The switching ofthe bit lines is effected by transistors Q71 to Q74 controlled bysignals S1 to S4. As a result, like the sixth embodiment, the patternarea can be reduced.

[0151] Moreover, since a sense amplifier is shared by a plurality ofadjacent bit lines, a sense amplifier, which is relatively difficult tosituate, can be provided easily in a pattern layout of the chip. Thisadvantage is enhanced by the combination with the aforementionedforcible inversion type sense amplifier. Specifically, in the forcibleinversion type sense amplifier, the forcible inversion means isconnected to the node of the flip-flop which is located on the sideopposite to the bit line, and consequently wiring is complex. If thesense amplifier is shared by every four bit lines, wiring can be madeeasily with allowance. From the standpoint of design, it is desirable togroup the bit lines in units of four.

[0152] The circuit configurations of the first to seventh embodiment inthe case where NAND-type memory cells are used have been describedabove. In these example, (1) the bit line is set at 0V when thethreshold is shifted in the write mode, and the latch data in theflip-flop circuit is inverted if the bit line remains at 5V afterread-out in the verify mode.

[0153] There may be other cases (2) to (4):

[0154] (2) The bit line is set at 0V when the threshold is shifted inthe write mode, and the latch data in the flip-flop circuit is invertedif the potential of the bit line reaches 0V after read-out in the verifymode (for example, a NOR-type memory cell structure wherein electronsare injected in the floating gate at the time of erase, and write iseffected by selectively extracting electrons from the drain and shiftingthe threshold to the negative side).

[0155] (3) The bit line is set at 5V when the threshold is shifted inthe write mode, and the latch data in the flip-flop circuit is invertedif the potential of the bit-line remains 5V after read-out in the verifymode (for example, a NOR-type memory cell structure wherein electronsare extracted from the floating gate at the time of erase, and write iseffected by selectively injecting electrons from the drain and shiftingthe threshold to the positive side).

[0156] (4) The bit line is set at 5V when the threshold is shifted inthe write mode, and the latch data in the flip-flop circuit is invertedif the potential of the bit line reaches 0V after read-out in the verifymode (for example, a NAND-type memory cell structure wherein electronsare injected in the floating gate at the time of erase, and write iseffected by selectively extracting electrons from the drain and shiftingthe threshold to the negative side).

[0157] The case (2) is illustrated in FIGS. 51 to 74. FIGS. 51 to 54 arecircuit diagrams showing main parts of applied examples corresponding tothe first embodiment, FIGS. 55 to 62 are circuit diagrams showing mainparts of applied examples of the second embodiment, FIGS. 63 to 66 arecircuit diagrams showing main parts of applied examples of the thirdembodiment, and FIGS. 67 to 74 are circuit diagrams showing main partsof applied examples corresponding to the fourth embodiment. Theoperations of these circuits are the same as those of theabove-described embodiments, and therefore a description thereof isomitted.

[0158] The case (3) is illustrated in FIGS. 75 to 98. FIGS. 75 to 78 arecircuit diagrams showing main parts of applied examples corresponding tothe first embodiment, FIGS. 79 to 86 are circuit diagrams showing mainparts of applied examples of the second embodiment, FIGS. 87 to 90 arecircuit diagrams showing main parts of applied examples of the thirdembodiment, and FIGS. 91 to 98 are circuit diagrams showing main partsof applied examples corresponding to the fourth embodiment. Theoperations of these circuits are the same as those of theabove-described embodiments, and therefore a description thereof isomitted FIGS. 99 to 102 show examples of the structure of the butchverify circuit. These examples correspond to the fifth embodiment, andtherefore a description thereof is omitted.

[0159] The case (4) is illustrated in FIGS. 103 to 126. FIGS. 103 to 106are circuit diagrams showing main parts of applied examplescorresponding to the first embodiment, FIGS. 107 to 114 are circuitdiagrams showing main parts of applied examples of the secondembodiment, FIGS. 115 to 118 are circuit diagrams showing main parts ofapplied examples of the third embodiment, and FIGS. 119 to 126 arecircuit diagrams showing main parts of applied examples corresponding tothe fourth embodiment. The operations of these circuits are the same asthose of the above-described embodiments, and therefore a descriptionthereof is omitted.

[0160]FIG. 127 is a circuit diagram showing the structure of a mostdesirable embodiment of the present invention. A portion in a block 25has a structure similar to that shown in FIG. 25. Specifically, when thelevel of signal φR rises, the node. BN of the flip-flop circuit 1 is setat “1”. If the level of signal φ3 rises in the state in which the bitline BL is at “1”, the flip-flop circuit 1 is inverted.

[0161] As has been described above, in the actual applied mode, severalthousand bit-by-bit verify-circuits are arranged in parallel. Whenread-out pulses φ3 are input in the state in which all bit lines are at“1”, all flip-flop circuits 1 are inverted. At this time, athrough-current flows in the flip-flop circuit 1, and the powerconsumption of the chip may increase or the source potential of theP-channel transistor Q33 may decrease due to wiring resistance. As aresult, the operation may become unstable.

[0162] The P-channel transistors Q35 and Q36 connected between thetransistors Q31 and Q33 and the power supply prevent the aboveundesirable operation and also prevent the through-current of apredetermined level or above from flowing. The gates of the transistorsare separated to realize flexible structure. That is, when anintermediate potential is input to the bit line, a large current flowsthrough the transistor Q36. Thus, the through-current is reduced byincreasing the gate potential of the transistor Q36, and the gatepotential of the transistor Q35 is lowered to enhance stability of theflip-flop circuit 1. Needless to say, the gates may be commonly used inconsideration of the specifications, or the conductance may becontrolled by the dimension of the P-channel MOS transistor.

[0163] If the through-current is reduced by the transistor Q35, thethreshold of the bit line potential for inverting the flip-flop circuit1 can be set in the vicinity of the threshold value of the transistorQ7, and influence of noise due to capacitance between bit lines can bedecreased.

[0164] A high voltage is applied to the bit line at the time ofprogramming/erasure. If conventional means for cutting off high voltageis adopted by inserting a depletion type MOS transistor Q37 between thebit line and the input terminal of the sense amplifier, the senseamplifier circuit can be constituted by low-voltage type transistors.Accordingly, the area occupied by the circuit elements can be reducedand the performance of the circuit can be enhanced.

[0165] The data in the flip-flop circuit 1 is read out to the IO linevia the transfer gate to which a column decode signal CS is input. Ifthe potential of the IO line is fully swung from the outside, desireddata can be written in the flip-flop circuit.

[0166] Electric current flowing from the IO/BIO line to the bit line canbe measured by setting the bit line in the selected state, setting thepotential of the node BN at “0” via the IO/BIO line, and setting thetransistor Q35 in the off state. The bit line current is a currentflowing to the cell or a leak current due to defects. With thisfunction, device information of the memory can be exactly acquired.

[0167] According to the above embodiment, the sense amplifier circuit isrealized wherein the bit-by-bit verify operation can be performed,influence of noise is very low, power consumption is low, and a testfunction is provided.

[0168] Although mentioned in the above description, the presentinvention is applicable not only to the NAND type EEPROM cell but to theNφR type EEPROM. FIG. 28 is a circuit diagram showing a circuit whereina NφR type memory cell is adopted in the structure shown in FIG. 115.For example, a memory cell having a selector transistor, which makes useof FN (Fowler-Nordheim) tunnel current for erase and write operations,is used. The reason is that write operations can be simultaneouslyeffected in a great number of cells (e.g. about 4000 bits) which makeuse of tunnel current for write operations. Thus, the effect of thebit-by-bit verify by the present invention can be exhibited to amaximum. It is more desirable to provide the selector transistor,because the drain stress of each transistor with floating gate isreduced. In the cell portion shown in FIG. 128, “erase” is defined bythe state in which electrons are injected in the floating gate at a timeand the threshold is increased. The write operation is performed in thefollowing manner. A voltage is applied to a selector gate SL0 and theselector transistor is turned on. Then, a positive bias voltage isapplied to the drain of the transistor in which data is to be written,and a negative bias voltage is applied to the control gate (one of wordlines WL0, WL1 . . . ) of the selected transistor. Thereby, electrons inthe floating gate of the selected bit are released to lower thethreshold value. At this time, if the electrons are released from thefloating gate excessively and the threshold value decreases to 0V orless, a current flows in the non-selected word line and data in theselected cell cannot be read. For this reason, like the NAND type cell,the stable operation can be expected by performing the bit-by-bit verifyoperation and writing “1”, data while sensing the threshold value. FIG.129 should be referred to with respect to the definition of thethreshold value distribution.

[0169] In FIG. 128, when data is to be written in the selected cell Mil(i.e. when electrons are to be released from the floating gate), thecircuit is reset such that the bit line-side node of the flip-flopcircuit 1 of the forcible inversion type sense amplifier is set at “H”level. This can be realized by using a reset transistor (not shown) orloading data from the outside via a column gate. In this state, thepower supply for the flip-flop circuit 1 is set at high potential, e.g.about 7V, a high bias voltage is applied to the drain, and a negativebias voltage of about −10V is applied to the word line WL0. Thereby,electrons are released from the floating gate of the selected cell. Inthe subsequent verify operation, φ2 is set at “L” to turn off thetransistor Q4 and SL0 is set at “L” to turn off the selector transistorQ05. In this state, WL0 is set at a predetermined verify potential, andthe bit line BL is precharged by the transistor Q3 Thereafter, theselector transistor Q05 is turned on to set the bit line in thefree-running state. At this time, if the threshold value is lower thanthe verify potential, the bit line potential decreases and “H” signal isoutput from the inverter 50. Accordingly, if φ3 is set at “H” at acertain timing, the flip-flop 1 is forcibly inverted, and the bitline-side node is set at “L”. If this node is at “L”, the electrons inthe floating gate are not released even if the negative bias is appliedto the word line at the time of write, since the drain remains at 0V. Onthe other hand; if the threshold value of the cell is greater than theverify potential, the bit line pre-charge level is maintained. Thus, theflip-flop circuit 1 is not inverted, and the write operation isperformed again. In the case where the selected cell needs to remain inthe erase state, the cell keeps the threshold value in the erase state,if data is loaded to set the bit line (BL)-side node of the flip-flopcircuit 1 at the “L” level, because no potential is applied to thedrain.

[0170] A normal read-out operation is performed by applying a properpotential (e.g. Vcc) to the control gate of the cell, instead of theverify potential, and by performing the same operation as the verifyoperation. As stated above, the present invention is applicable to theNOR-type EEPROM of the type in which the threshold is lowered at thetime of write, and the same advantage as with the NAND-type device canbe obtained. In particular, if this invention is applied to the cellwhich makes use of FN tunnel current at the time of write, the merit ofmulti-bit simultaneous write can be obtained, and the cell using theselector transistor is desirable in terms of stress.

[0171] As has been described above, according to the present invention,when a single write/verify operation has been completed, the data in theflip-flop circuit is inverted by the forcible inversion means (datasetting circuit). As a result, the bit-by-bit verify operation isrealized.

[0172] Moreover, unlike the prior art, the bit line potential is notvaried, since the bit line potential is applied only to the forcibleinversion means (data setting circuit). Besides, the through-currentpath is not provided, and the power consumption is not increased.

[0173] Additional advantages and modifications will readily occur tothose skilled in the art. Therefore, the invention in its broaderaspects is not limited to the specific details, and representativedevices, shown and described herein. Accordingly, various modificationsmay be made without departing from the spirit or scope of the generalinventive concept as defined by the appended claims and theirequivalents.

What is claimed is:
 1. A non-volatile semiconductor memory device havinga verify mode, said device comprising: flip-flop circuit means forholding latch data in one of first and second states; bit line means;setting means for setting said bit line means to a reference potential;coupling means for coupling said flip-flop circuit means and said bitline means; non-volatile memory cell means, connected to said bit linemeans and having a MOS transistor structure, for storing data when athreshold thereof is set in one of first and second threshold ranges,wherein at the is time of a write mode said threshold of the memory cellmeans is shifted from the first threshold range towards the secondthreshold range while said flip-flop circuit means remains in the firststate and the shift of the threshold is not effected while saidflip-flop circuit means remains in the second state, and at the time ofthe verify mode following the write mode said bit line means is kept atsaid reference potential by said setting means while the thresholdremains in the second threshold range; and data setting circuit meansfor providing, at the time of the verify mode, said flip-flop circuitmeans with a path for supplying a latch potential when said bit linemeans is set at the reference potential and setting the flip-flopcircuit means in the second state irrespective of the state prior to theverify mode.
 2. The device according to claim 1 , wherein said bit linemeans comprises a bit line, said flip-flop circuit means comprises aflip-flop circuit having at least first and second signal nodes, and theconnection of said coupling means is controlled by at least oneswitching element, said switching element being turned off at the timeof the verify mode, thereby electrically disconnecting said bit linefrom said flip-flop circuit.
 3. The device according to claim 2 ,wherein said flip-flop circuit includes at least two CMOS invertercircuits having their input and output terminals connected in parallelin opposite directions, said data setting circuit means includes MOStransistor circuit means having a current path connected between one ofthe first and second signal nodes of the flip-flop circuit and a powersupply node for providing said latch potential, and said MOS transistorcircuit means includes at least a first MOS transistor having a gatecontrolled in accordance with a signal of said bit line.
 4. The deviceaccording to claim 3 , wherein the relationship between a conductancegmN of said MOS transistor circuit means and a conductance gmP of a MOStransistor within said CMOS inverter circuit for charging/dischargingone of the first and second signal nodes of the flip-flop circuit isgiven by gmN/gmP>1.8
 5. The device according to claim 2 , wherein saidflip-flop circuit includes at least two CMOS inverter circuits havingtheir input and output terminals connected in parallel in oppositedirections, said data setting circuit means includes a second MOStransistor having a current path connected between one of the first andsecond signal nodes of the flip-flop circuit and a power supply node forproviding said latch potential in series with a first MOS-transistor, agate of said first MOS transistor is controlled in accordance with asignal of said bit line, a control signal is input to a gate of saidsecond MOS transistor, and said second MOS transistor is turned on atthe time of the verify mode.
 6. The device according to claim 5 ,wherein the relationship between an equivalent conductance gmN of saidfirst and second MOS transistors and a conductance gmP of a MOStransistor within said CMOS inverter circuit for charging/dischargingone of the first and second signal nodes of the flip-flop circuit isgiven by gmN/gmP>1.8
 7. The device according to claim 5 , wherein saidfirst MOS transistor is provided on said flip-flop circuit side, andsaid second MOS transistor is provided on said power supply node side.8. The device according to claim 5 , wherein said second VOS transistoris provided on said flip-flop circuit side, and said first MOStransistor is provided on said power supply node side.
 9. The deviceaccording to claim 3 , wherein said MOS transistor circuit meansincludes a third MOS transistor having a current path connected inseries between said first MOS transistor and one of the first and secondsignal nodes of the flip-flop circuit, and a fourth MOS transistorhaving a current path connected in series between said first MOStransistor and said power supply node, said third and fourth MOStransistors being turned on at the time of the verify mode when thegates of said third and fourth MOS transistors are supplied with controlsignals.
 10. The device according to claim 3 , wherein said MOStransistor circuit means includes transfer control means for enabling agate control operation of the first MOS transistor at the time of theverify mode.
 11. The device according to claim 1 , further comprisingreset means for providing another path for supplying a reset potentialto said flip-flop circuit at the time of a reset mode, and setting saidflip-flop circuit means in the first state.
 12. The device according toclaim 11 , wherein one of a ground potential and a power supplypotential Is supplied to a power supply node of said path for supplyingthe latch potential, and one of a ground potential and a power supplypotential is supplied to a power supply node of said another path forsupplying the reset potential.
 13. The device according to claim 1 ,wherein said bit line means comprises a plurality of bit lines, saidflip-flop circuit means comprises a plurality of flip-flop circuitshaving first and second signal nodes, and said coupling means comprisesa plurality of switching elements to be turned off at the time of theverify mode for electrically disconnecting said flip-flop circuit froman associated one of said bit lines, said coupling means controllingconnection between said bit lines and said-flip-flop circuits.
 14. Thedevice according to claim 13 , wherein each of said flip-flop circuitsis shared by at least two of said bit lines.
 15. The device according toclaim 1 , wherein said bit line means comprises a plurality of bitlines, said flip-flop circuit means comprises a plurality of flip-flopcircuits each having first and second signal nodes, and said couplingmeans comprises a plurality of switching elements to be turned off atthe time of the verify mode for electrically disconnecting saidflip-flop circuit from an associated one of said bit lines, saidcoupling means controlling connection between said bit lines and saidflip-flop circuits, and wherein said device further comprising verifysensing means for sensing completion of a verify operation in the verifymode for data in each of the memory cells.
 16. The device according toclaim 15 , wherein said verify sensing comprises a shared verify linefor obtaining a sense signal only when the potential at one of the firstand second signal nodes of each of s~aid flip-flop circuits is equal.17. The device according to claim 1 , wherein said non-volatile memorycell means makes use of an FN (Fowler-Nordheim) tunnel current at thetime of the write mode.
 18. The device according to claim 17 , whereinsaid non-volatile memory cell means includes a plurality of MOStransistors each having a floating gate, and selector transistor meansprovided between said MOS transistors and said bit lines.
 19. Anon-volatile semiconductor memory device comprising: flip-flop circuitmeans for holding latch data in one of first and second states; bit linemeans; setting means for setting said bit line means to a referencepotential; coupling means for coupling said flip-flop circuit means andsaid bit line means; reset means for providing a first path forsupplying a reset potential to said flip-flop circuit means at the timeof a reset mode, and keeping said flip-flop circuit means in the firststate; non-volatile memory cell means of a MOS transistor construction,connected to said -bit line means, for storing data when a thresholdthereof is set in one of first and second threshold ranges, saidnon-volatile memory cell means maintaining said bit line means at thereference potential by said setting means, when said threshold value isin said second threshold range, at the time of a read mode followingsaid reset mode; and data setting circuit means for providing a secondpath for supplying a latch potential to said flip-flop circuit meanswhen said bit line means is at said reference potential at the time ofthe read mode, and keeping said flip-flop circuit means in the secondstate.
 20. The device according to claim 19 , wherein one of a groundpotential and a power supply potential is supplied to a first powersupply node of said first path for supplying the reset potential, andone of a ground potential and a power supply potential is supplied to asecond power supply node of said second path for supplying the latchpotential.
 21. The device according to claim 20 , wherein said bit linemeans comprises a bit line, said flip-flop circuit means comprises aflip-flop circuit having at least first and second signal nodes, and theconnection of said coupling means is controlled by at least oneswitching element, said switching element being turned off at the timeof the read mode, thereby electrically disconnecting said bit line fromsaid flip-flop circuit.
 22. The device according to claim 21 , whereinsaid flip-flop circuit includes at least two CMOS inverter circuitshaving their input and output terminals connected in parallel inopposite directions, said data setting circuit means includes a MOStransistor circuit means having a current path connected between one ofthe first and second signal nodes of the flip-flop circuit and the powersupply node of the second path, and said MOS transistor circuit meansincludes at least a first MOS transistor having a gate controlled inaccordance with a signal of said bit line.
 23. The device according toclaim 22 , wherein the relationship between a conductance gmN of saidMOS transistor circuit means and a conductance gmP of a MOS transistorwithin said CMOS inverter circuit for charging/discharging one of thefirst and second signal nodes of the flip-flop circuit is given bygmN/gmP>1.8
 24. The device according to claim 21 , wherein saidflip-flop circuit includes at least two CMOS inverter circuits havingtheir input and output terminals connected in parallel in oppositedirections, said data setting circuit means includes a second MOStransistor having a current path connected between one of the first andsecond signal nodes of the flip-flop circuit and the second power supplynode in series with a first MOS transistor, a gate of said first MOStransistor is controlled in accordance with a signal of said bit line, acontrol signal is input to a gate of said second MOS transistor, andsaid second MOS transistor is turned on at the time of the verify mode.25. The device according to claim 24 , wherein the relationship betweenan equivalent conductance gmN of said first and second MOS transistorsand a conductance gmP of a MOS transistor within said CMOS invertercircuit for charging/discharging one of the first and second signalnodes of the flip-flop circuit is given by gmN/gmP>1.8
 26. The deviceaccording to claim 24 , wherein said first MOS transistor is provided onsaid flip-flop circuit side, and said second MOS transistor is providedon said second power supply node side.
 27. The device according to claim24 , wherein said second MOS transistor is provided on said flip-flopcircuit side, and said first MOS transistor is provided on said secondpower supply node side.
 28. The device according to claim 22 , whereinsaid MOS transistor circuit means includes a third MOS transistor havinga current path connected in series between said first MOS transistor andone of the first and second signal nodes of the flip-flop circuit, and afourth MOS transistor having a current path connected in series betweensaid first MOS transistor and said second power supply node, said thirdand fourth MOS transistors being turned on at the time of the read modewhen the gates of said third and fourth MOS transistors aresupplied-with control signals.
 29. The device according to claim 22 ,wherein said MOS transistor circuit means includes transfer controlmeans for enabling a gate control operation of the first MOS transistorat the time of the read mode.
 30. The device according to claim 19 ,wherein said bit line means comprises a plurality of bit lines, saidflip-flop circuit means comprises a plurality of flip-flop circuits eachhaving first and second signal nodes, and said coupling means comprisesa plurality of switching elements to be turned off at the time of theread mode for electrically disconnecting said flip-flop circuit from anassociated one of said bit lines, said coupling means controllingconnection between said bit lines and said flip-flop circuits.
 31. Thedevice according to claim 30 , wherein each of said flip-flop circuitsis shared by at least two of said bit lines.
 32. The device according toclaim 19 , wherein said bit line means comprises a plurality of bitlines, said flip-flop circuit means comprises a plurality of flip-flopcircuits each having first and second signal nodes, and said couplingmeans comprises a plurality of switching elements to be turned off atthe time of the verify mode for electrically disconnecting saidflip-flop circuit from an associated one of said bit lines, saidcoupling means controlling connection between said bit lines and saidflip-flop circuits, and wherein said device further comprising datainput/output circuit means for enabling a read operation in the readmode and a write operation in the write operation for data of eachmemory cell.
 33. The device according to claim 32 , wherein said datainput/output circuit means includes column gates connected to the firstand second signal nodes of the flip-flop circuits.
 34. The deviceaccording to claim 19 , wherein said non-volatile memory cell meansmakes use of an FN (Fowler-Nordheim) tunnel current at the time of thewrite mode.
 35. The device according to claim 34 , wherein saidnon-volatile memory cell means includes a plurality of MOS transistorseach having a floating gate, and selector transistor means providedbetween said MOS transistors and said bit lines.
 36. A non-volatilesemiconductor memory device comprising: flip-flop circuit means forholding latch data in one of first and second states; reset means forproviding a first path for supplying a reset potential to said flip-flopcircuit means at the time of a reset mode, and keeping said flip-flopcircuit means in the first state; bit line means; setting means forsetting said bit line means to a reference potential; coupling means forcoupling said flip-flop circuit means and said bit line means;non-volatile memory cell means, connected to said bit line means andhaving a MOS transistor structure, for storing data when a thresholdthereof is set in one of first and second threshold ranges, wherein atthe time of a write mode said threshold of the memory cell means isshifted from the first threshold range towards the second thresholdrange while said flip-flop circuit means remains in the first state andthe shift of the threshold is not effected while said flip-flop circuitmeans remains in the second state, and at the time of a verify modefollowing the write mode and at the time of a read mode following thereset mode said bit line means is kept at said reference potential bysaid setting means while the threshold remains in the second thresholdrange; and data setting circuit means for providing a second path forsupplying a latch potential to said flip-flop circuit means when saidbit line means is at said reference potential at the time of the verifymode and the read mode, and keeping said flip-flop circuit means in thesecond state irrespective of the state prior to the verify mode.
 37. Thedevice according to claim 36 , wherein one of a ground potential and apower supply potential is supplied to a first power supply node of saidfirst path for supplying the reset potential, and one of a groundpotential and a power supply potential is supplied to a second powersupply node of said second path for supplying the latch potential. 38.The device according to claim 37 , wherein said bit line means comprisesa bit line, said flip-flop circuit means comprises a flip-flop circuithaving at least first and second signal nodes, and the-connection ofsaid coupling means is controlled by at least one switching element,said switching element being turned off at the time of the read mode,thereby electrically disconnecting said bit line from said flip-flopcircuit
 39. The device according to claim 38 , wherein said flip-flopcircuit includes at least two CMOS inverter circuits having their inputand output terminals connected in parallel in opposite directions, saiddata setting circuit means includes a MOS transistor circuit meanshaving a current path connected between one of the first and secondsignal nodes of the flip-flop circuit and the second power supply node,and said MOS transistor circuit means includes at least a first MOStransistor having a gate controlled in accordance with a signal of saidbit line.
 40. The device according to claim 39 , wherein therelationship between a conductance gmN of said MOS transistor circuitmeans and a conductance gmP of a MOS transistor within said CMOSinverter circuit for charging/discharging one of the first and secondsignal nodes of the flip-flop circuit is given by gmN/gmP>1.8
 41. Thedevice according to claim 38 , wherein said flip-flop circuit includesat least two CMOS inverter circuits having their input and outputterminals connected in parallel in opposite directions, said datasetting circuit means includes a first MOS transistor and a second MOStransistor having current paths connected in series between one of thefirst and second signal nodes of the flip-flop circuit and said secondpower supply node, a gate of said first MOS transistor is controlled inaccordance with a signal of said bit line, a control signal is input toa gate of said second MOS transistor, and said second MOS transistor )sturned on at the time of the verify mode.
 42. The device according toclaim 41 , wherein the relationship between an equivalent conductancegmN of said first and second MOS transistors and a conductance gmP of aMOS transistor within said CMOS inverter circuit forcharging/discharging one of the first and second signal nodes of theflip-flop circuit is given by gmN/gmP>1.8
 43. The device according toclaim 39 , wherein said first MOS transistor is provided on saidflip-flop circuit side, and said second MOS transistor is provided onsaid second power supply node side.
 44. The device according to claim 41, wherein said second MOS transistor is provided on said flip-flopcircuit side, and said first MOS transistor is provided on said secondpower supply node side.
 45. The device according to claim 39 , whereinsaid MOS transistor circuit means includes a third MOS transistor havinga current path connected in series between said first MOS transistor andone of the first and second signal nodes of the flip-flop circuit, and afourth MOS transistor having a current path connected in series betweensaid first MOS transistor and said second power supply node, said thirdand fourth MOS transistors being turned on at the time of the read modewhen the gates of said third and fourth MOS transistors are suppliedwith control signals.
 46. The device according to claim 39 , whereinsaid MOS transistor circuit means includes transfer control means forenabling a gate control operation of the first MOS transistor at thetime of the verify mode.
 47. The device according to claim 36 , whereinsaid bit line means comprises a plurality of bit lines, said flip-flopcircuit means comprises a plurality of flip-flop circuits having firstand second signal nodes, and said coupling means comprises a pluralityof switching elements to be turned off at the time of the read mode forelectrically disconnecting said flip-flop circuit from an associated oneof said bit lines, said coupling means controlling connection betweensaid bit lines and said flip-flop circuits.
 48. The device according toclaim 47 , wherein each of said flip-flop circuits is shared by at leasttwo of said bit lines.
 49. The device according to claim 36 , whereinsaid bit line means comprises a plurality of bit lines, said flip-flopcircuit means comprises a plurality of flip-flop circuits each havingfirst and second signal nodes, and said coupling means comprises aplurality of switching elements to be turned off at the time of theverify mode for electrically disconnecting said flip-flop circuit froman associated one of said bit lines, said coupling means controllingconnection between said bit lines and said flip-flop circuits, andwherein said device further comprising verify sensing means for sensingcompletion of a verify operation in the verify mode for data in each ofthe memory cells.
 50. The device according to claim 49 , wherein saidverify sensing comprises a shared verify line for obtaining a sensesignal only when the potential at one of the first and second signalnodes of each of said flip-flop circuits is equal.
 51. The deviceaccording to claim 36 , wherein said non-volatile memory cell meansmakes use of an FN (Fowler-Nordheim) tunnel current at the time of thewrite mode.
 52. The device according to claim 51 , wherein saidnon-volatile memory cell means includes a plurality of MOS transistorseach having a floating gate, and selector transistor means providedbetween said MOS transistors and said bit lines.
 53. A non-volatilesemiconductor memory device having a verify mode, said devicecomprising: bit line means; non-volatile memory cell means connected tosaid bit line means; setting means for setting said bit line means to areference potential; flip-flop circuit means for holding latch-data inone of first and second states; coupling means for coupling saidflip-flop circuit means and said bit line means; latch control means forsetting the latch data in said flip-flop circuit means in accordancewith data to be written in said memory cell means; and data settingcircuit means for forcibly inverting the latch data of the flip-flopcircuit means in response to the reference potential of the bit linemeans when the reference potential of the bit line means reaches apredetermined voltage value in the verify mode for said memory cellmeans.
 54. The device according to claim 53 , further comprising resetmeans for initializing said latch control means.
 55. The deviceaccording to claim 53 , wherein the connection of said coupling means iscontrolled by at least one switching element, said switching elementbeing turned off at the time of the verify mode, thereby electricallydisconnecting said bit line from said flip-flop circuit means.
 56. Thedevice according to claim 53 , wherein said flip-flop circuit meansincludes at least two CMOS inverter circuits having their input andoutput terminals connected in parallel in opposite directions and havingfirst and second signal nodes, said data setting circuit means includesMOS transistor circuit means having a current path connected between oneof the first and second signal nodes of the flip-flop circuit and apower supply node for providing a latch potential, and said MOStransistor circuit means includes at least a first MOS transistor havinga gate controlled in accordance with a signal of said bit line.
 57. Thedevice according to claim 56 , wherein the relationship between aconductance gmN of said MOS transistor circuit means and a conductancegmP of a MOS transistor within said CMOS inverter circuit forcharging/discharging one of the first and second signal nodes of theflip-flop circuit is given by gmN/gmP>1.8
 58. The device according toclaim 53 , wherein said flip-flop circuit means includes at least twoCMOS inverter circuits having their input and output terminals connectedin parallel in opposite directions, said data setting circuit meansincludes a second MOS transistor having a current path connected betweenone of the first and second signal nodes of the flip-flop circuit and apower supply node for providing a latch potential in series with a firstMOS transistor, a gate of said first MOS transistor is controlled inaccordance with a signal of said bit line, a control signal is input toa gate of said second MOS transistor, and said second MOS transistor isturned on at the time of the verify mode.
 59. The device according toclaim 58 , wherein the relationship between an equivalent conductancegmN of said first and second MOS transistors and a conductance gmP of aMOS transistor within said CMOS inverter circuit forcharging/discharging one of the first and second signal nodes of theflip-flop circuit is given by gmN/gmP>1.8
 60. The device according to-claim 58 , wherein said first MOS transistor is provided on saidflip-flop circuit means side, and said second MOS transistor is providedon said power supply node side.
 61. The device according to claim 58 ,wherein said second MOS transistor is provided on said flip-flop circuitmeans side, and said first MOS transistor is provided on said powersupply node side.
 62. The device according to claim 56 , wherein saidMOS transistor circuit means includes a third MOS transistor having acurrent path connected in series between said first MOS transistor andone of the first and second signal nodes of the flip-flop circuit, and afourth MOS transistor having a current path connected in series betweensaid first MOS transistor and said power supply node, said third andfourth MOS transistors being turned on at the time of the verify modewhen the gates of said third and fourth MOS transistors are suppliedwith control signals.
 63. The device according to claim 56 , whereinsaid MOS transistor circuit means includes transfer control means forenabling a gate control operation of the first MOS transistor at thetime of the verify mode.
 64. The device according to claim 53 , whereinsaid non-volatile memory cell means makes use of an FN (Fowler-Nordheim)tunnel current at the time of a write mode preceding the verify mode.65. The device according to claim 53 , wherein said memory cell meansconstitutes a NAND type flash memory.
 66. The device according to claim53 , wherein said non-volatile memory cell means constitutes a NAND typeflash memory and makes use of an. FN (Fowler-Nordheim) tunnel current atthe time of a write mode preceding the verify mode.